lowRISC / lowRISC/opentitan

[test-triage, darjeeling] chip_sw_keymgr_dpe_key_derivation

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Component:TestTriage
Dominant language
SystemVerilog
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Description

### Hierarchy of regression failure

Chip Level

### Failure Description

```
* `UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:490) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*])` has 1 failures:
* Test chip_sw_keymgr_dpe_key_derivation has 1 failures.
* 0.chip_sw_keymgr_dpe_key_derivation.1\
Line 1550, in log /home/doreis/git/opentitan.git/master/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

UVM_ERROR @ 6130.183901 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:490) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (88491710092124497810122701312756897961155547385836369027721156125958377646664 [0xc3a4887195e77cf49ccdaebc349733e71788140a54e5e7f19e3575d73dd52a48] vs 79032847161637854013771212485155359191343552179835959862065675497230843893813 [0xaebb019bfb9cbd7abcba983dfac3254f0cd7cc408e5f5d2700703e29c159d835])
UVM_INFO @ 6130.183901 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---

```

### Steps to Reproduce

- GitHub Revision: master
```sh
util/dvsim/dvsim.py hw/top_darjeeling/dv/chip_sim_cfg.hjson --tool xcelium -v m --fi 1 -i chip_sw_keymgr_dpe_key_derivation

```

### Tests with similar or related failures

- [ ] chip_sw_keymgr_dpe_key_derivation

Contributor guide

Open the contributing guide

Research direction

Reproduce the failure with the provided dvsim command, then inspect chip_sw_keymgr_dpe_key_derivation_vseq.sv around line 490 and the referenced run.log entry. Trace the reported digest mismatch and confirm the test completes without the UVM_ERROR.

Written by the indexing model from the issue text.

Assessment

Domain
embedded-iot, testing
Issue type
Bug
Difficulty
4/5
Estimated time
3-5 days
Activity status
Stale
Clarity
Needs clarification
Newbie friendliness
32/100

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