lowRISC / lowRISC/opentitan

[test-triage, darjeeling] chip level tests needs a ROM.

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Component:TestTriage
Dominant language
SystemVerilog
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Description

### Hierarchy of regression failure

Chip Level

### Failure Description

```
* Test chip_sw_example_manufacturer has 1 failures.
* 0.chip_sw_example_manufacturer.1\
Log /home/doreis/git/opentitan.git/master/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_example_manufacturer/latest/run.log

Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
@@+hooks+manufacturer_test_hooks//:example_test_sim_dv (cd133b) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.562s, Critical Path: 0.00s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
make: *** [/home/doreis/git/opentitan.git/master/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

```

### Steps to Reproduce

- GitHub Revision: master
- dvsim invocation command to reproduce the failure, inclusive of build and run seeds:
```sh
util/dvsim/dvsim.py hw/top_darjeeling/dv/chip_sim_cfg.hjson --tool xcelium -v m --fi 1 -i\
chip_sw_example_concurrency \
chip_sw_example_manufacturer \
chip_sw_example_rom
```

### Tests with similar or related failures

- [ ] chip_sw_example_concurrency
- [ ] chip_sw_example_manufacturer
- [ ] chip_sw_example_rom
- [ ] chip_sw_power_virus
- [ ] base_rom_e2e_smoke

Contributor guide

Open the contributing guide

Research direction

Start with the failing target in the provided run log, then inspect hw/top_darjeeling/dv/chip_sim_cfg.hjson, util/dvsim/dvsim.py, and hw/dv/tools/dvsim/sim.mk. Reproduce the failure with the listed dvsim command and determine why the chip-level targets are incompatible. Done means the named chip-level tests build and run without this failure.

Written by the indexing model from the issue text.

Assessment

Domain
build-system, embedded-iot, testing
Issue type
Bug
Difficulty
4/5
Estimated time
3-5 days
Activity status
Stale
Clarity
Needs clarification
Newbie friendliness
25/100

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