[test-triage, darjeeling] kJitterEnable.dat error
Open
@alees24 is already working on this.
Since Apr 4, 2025.
Component:TestTriage
- Dominant language
- SystemVerilog
- Stars
- 3.6k
- Forks
- 1.1k
- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
Hierarchy of regression failure
Chip Level
Failure Description
`UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"` has 1 failures:
* Test chip_sw_aes_enc_jitter_en has 1 failures.
* 0.chip_sw_aes_enc_jitter_en.1\
Line 1467, in log /home/doreis/git/opentitan.git/master/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_aes_enc_jitter_en/latest/run.log
UVM_FATAL @ 10.120001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Steps to Reproduce
- GitHub Revision: master
- dvsim invocation command to reproduce the failure, inclusive of build and run seeds:
util/dvsim/dvsim.py hw/top_darjeeling/dv/chip_sim_cfg.hjson --tool xcelium -v m --fi 1 -i chip_sw_kmac_mode_kmac_jitter_en
Tests with similar or related failures
- chip_sw_aes_enc_jitter_en
- chip_sw_kmac_mode_kmac_jitter_en
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Assessment
This issue has not been assessed yet.