lowRISC / lowRISC/opentitan

[test-triage, darjeeling] chip_sw_plic_all_irqs

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#26,803 0 comments 0 reactions 1 assignee Claimed by @engdoreis View on GitHub
Component:TestTriage
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SystemVerilog
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Description

### Hierarchy of regression failure

Chip Level

### Failure Description
```
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests/autogen/top_darjeeling:plic_all_irqs_test_sim_dv': no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- sw/device/tests/autogen/top_darjeeling
ERROR: no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- sw/device/tests/autogen/top_darjeeling
INFO: Elapsed time: 0.174s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
```

### Steps to Reproduce

- GitHub Revision: master
- dvsim invocation command to reproduce the failure, inclusive of build and run seeds:
```sh
util/dvsim/dvsim.py hw/top_darjeeling/dv/chip_sim_cfg.hjson --tool xcelium -v m --fi 1 -i chip_plic_all_irqs
```

### Tests with similar or related failures

- [ ] chip_sw_plic_all_irqs

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