[gpio/dv] Fully verify input period counter feature
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- Dominant language
- SystemVerilog
- Stars
- 3.6k
- Forks
- 1.1k
- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
PR #26351 adds input period counters to gpio, together with some minimal verification. To fully verify this feature, testplan items must be written, functional coverage defined, and the test needs to be more randomized to close coverage.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start with PR #26351 and its gpio input period counter changes. Define the required testplan items and functional coverage, then identify how the existing test can be randomized further. Done means the feature has documented testplan coverage and the randomized test closes the identified coverage gaps.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, testing
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 35/100