[Comportable IP] Register blocks should indicate if they are memories

@andreaskurth is already working on this.

Since Feb 26, 2025.

### Description

Currently memories are modelled as register blocks by IP and only the top level configuration specifies that they are memories. For example:
```javascript
// sram_ctrl.hjson
registers: {
regs: [
////////////////////////
// Ctrl / Status CSRs //
////////////////////////

{ name: "STATUS",
desc: "SRAM status register.",
swaccess: "ro",
hwaccess: "hrw",
hwqe: "false",
fields: ..
},
// ....
],
ram: [
// no CSRs defined here.
]
}
```
and
```javascript
{ name: "sram_ctrl_ret_aon",
type: "sram_ctrl",
clock_srcs: {clk_i: "io_div4", clk_otp_i: "io_div4"},
clock_group: "infra",
reset_connections: {rst_ni: "lc_io_div4", rst_otp_ni: "lc_io_div4"},
domain: ["Aon"],
param_decl: {
InstrExec: "0",
InstSize: "4096",
}
base_addrs: {
regs: {hart: "0x40500000"},
ram: {hart: "0x40600000"},
}
// Memory regions must be associated with a dedicated
// TL-UL device interface.
memory: {
ram: {
label: "ram_ret_aon",
swaccess: "rw",
data_intg_passthru: "true",
exec: "True",
byte_write: "True",
size: "0x1000"
}
}
},
```
This is not ideal in terms of model, especially for looks like the DT, because there is no guarantee that the `ram` register block is always going to be a memory. Ideally, the `sram_ctrl.hjson` file should indicate that the `ram` register block is in fact a memory.