[tlgen] Model bus bridges with address translation

Integrated designs have more complex interconnection networks than Earlgrey, but tlgen is currently only capable of modeling completely disjoint networks. Meanwhile, Darjeeling actually has bus bridges that create paths between address spaces--Device nodes in one address space are reachable by host nodes in another address space.

tlgen and topgen may need to be extended to model this connectivity, so artifacts may be generated appropriately. Address spaces are currently used as a proxy to determine what interrupts, alerts, etc. are relevant for a given host. However, a PLIC may sit in the host's address space, yet collect interrupt signals from devices in another address space. If that other address space is not reachable, this should yield an error! Otherwise, if the address spaces are bridged, then we would ideally be able to generate DV and software artifacts that can exercise those devices.

In addition, model proxy / filter modules, which don't change the address space but otherwise augment transactions somehow. Allow external xbars and model the xbar-xbar connection through toplevel.sv ports. The soc_proxy IP seems to fit into this category.

Indirectly prodded by #26275

Start by reading the tlgen and topgen implementations and the context in #26275. Trace how address spaces, host and device reachability, interrupts, alerts, and generated DV/software artifacts are currently modeled, then review toplevel.sv and soc_proxy for external xbar connections. Done should include a defined model for bridges, proxy/filter modules, and the required validation and generated artifacts.

Written by the indexing model from the issue text.