[pattgen,dv] The cnt_rollover test doesn't really work
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- SystemVerilog
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Description
### Description
As I understand it, this was supposed to be setting large `prediv` values and checking the counter worked properly. A good idea! Unfortunately, it doesn't actually sample the enormous 32-bit range for the register. (Maybe the spec changed over time)
Waiting 4 billion cycles is not a realistic approach(!) so we will need to force a value to be "near the top" during the simulation.
Reading that carefully, I also realised that the coverage tracking for this in `pattgen_cov_if` doesn't really make much sense. I think the author was explicitly looking to see the rollover, but does so by looking at the threshold values instead of the counters. Oops!
Contributor guide
Research direction
Locate the cnt_rollover test and the pattgen_cov_if coverage logic in the pattgen/dv area, then read how the counter and threshold values are sampled. Done means the simulation exercises a counter value near the 32-bit maximum without waiting billions of cycles, and coverage tracks the actual rollover behavior.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, testing-qa
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 45/100