lowRISC / lowRISC/opentitan

[Multitop, test] chip_sw_racl_smoketest

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Component:ChipLevelTest IP: Multitop:Autogen Priority:P2
Dominant language
SystemVerilog
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Description

- Tests should not depend on earlgrey constants. Try removing #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" and see what doesn't compile.
- Replace any dif__init with dif__init_from_dt to avoid TOP_EARLGREY__BASE_ADDR.
- Add //hw/top:dt to deps to get all device table libraries.
- Use bazel build //hw/top:dt_api_hdr and bazel build //hw/top:dt__hdr to see the autogenerated DT headers. The _src suffix shows the C files.
- Grep for kClockFreq.*. These are top-specific but don't come from a top_earlgrey header. Replace with dt_clock_frequency(...).
- For ISRs: replace peripheral = with dt_plic_id_to_instance_id and compare to the DT instance using dt__instance_id(dt__t).
- Again for ISRs, convert the plic IRQ ID to a block-specific ID with dt__irq_from_plic_id and switch on that.

The test chip_sw_racl_smoketest should run and pass for Ealrgrey and should build for Darjeeling.

Contributor guide

Open the contributing guide

Research direction

Start by locating the chip_sw_racl_smoketest sources and running the two Bazel DT header builds named in the issue. Review its top-specific includes, DIF initialization, clock lookups, and ISR handling against the generated DT APIs. Done means it passes for Earlgrey and builds for Darjeeling without Earlgrey constants.

Written by the indexing model from the issue text.

Assessment

Tech stack
c
Domain
embedded-iot, testing-qa
Issue type
Refactor
Difficulty
4/5
Estimated time
3-5 days
Activity status
Stale
Clarity
Mostly clear
Newbie friendliness
35/100

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