[topgen] Intermodule feature to assign default value to vector signal

If the dangling inter-module signal of an IP is a vector signal (width more than 1) and input, then topgen intermodule doesn't assign the value correctly.

Example:

```hjson
inter_signal_list: [
{ struct: "a",
type: "uni",
name: "a",
act: "rcv",
package: "pkg",
width: 2
}
]
```

Result from topgen:
```systemverilog
// top
mod u_mod (
.a_i (pkg::A_DEFAULT)
);
```

Expected result:

```systemverilog

pkg::a_t [1:0] mod_a;

mod u_mod (
.a_i(mod_a)
);

assign mod_a = {2{pkg::A_DEFAULT}};
```

CC: @msfschaffner @tjaychen