[chip-test] sleep_pin_wake inconsistent flow between DV and SiVal
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Component:ChipLevelTest
- Dominant language
- SystemVerilog
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Description
### Test point name
chip_sw_sleep_pin_wake
### Host side component
SystemVerilog+Rust
### OpenTitanTool infrastructure implemented
Yes
### Silicon Validation (SiVal)
Yes
### Emulation Targets
- [ ] None
- [x] CW310
- [ ] Hyperdebug + CW310
### Contact person
luismarques
### Description
The test `chip_sw_sleep_pin_wake` has inconsistent flow between DV and SiVal. In DV, make the vseq choose the sequence and communicate it to the vseq via backdoor symbol overwrites (to the same variables that sival uses).
See https://github.com/lowRISC/opentitan/pull/25365#pullrequestreview-2456779592
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