[earlgrey] issue: failed run code in sram
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- SystemVerilog
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Description
- **Modify** hw/top_earlgrey/dv/chip_smoketests.hjson : type change to '5', "SwTypeDebug" like below:
**sw_images**: ["//sw/device/tests:uart_smoketest:5:new_rules"]
Then check the 'uart_smoketest_sim_dv.dis' file, address map is 0x20000000, it is flash address area. Not sram address area.
- **test result**: run.log
UVM_FATAL @ 10010.708289 us: (chip_sw_uart_smoke_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.chip_sw_uart_smoke_vseq] wait timeout occurred!
- **check wave.fsdb**: pc jump to flash address area, the instruction is ffffffff.
How can I run code in sram? thanks!
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start with hw/top_earlgrey/dv/chip_smoketests.hjson and the uart_smoketest_sim_dv.dis address map, then review run.log and wave.fsdb around the timeout in chip_sw_uart_smoke_vseq.sv:24. Determine how the test should load and execute code in SRAM rather than jumping to 0x20000000 as flash, then verify the simulation completes without the UVM wait timeout.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, testing-qa
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Active
- Clarity
- Needs clarification
- Newbie friendliness
- 35/100