[lc_ctrl, dv] Tests to pass V3
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Component:DV
IP:lc_ctrl
Type:Signoff
- Dominant language
- SystemVerilog
- Stars
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- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
List of tests to be completed and (passing or waived) for V3
- [ ] Example 1
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
The issue identifies the lc_ctrl and dv areas and a V3 test list, but names no files, test entry points, or expected results. Start by locating the V3 tests for lc_ctrl and the item labeled Example 1. Done means each listed test is passing or explicitly waived.
Written by the indexing model from the issue text.
Assessment
- Domain
- testing
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100