lowRISC / lowRISC/opentitan

[earlgrey_1.0.0] Bitstream in Bazel cache outdated

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#25,166 1 comment 0 reactions 0 assignees View on GitHub
Component:FPGA
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SystemVerilog
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Description

@nmoroze and @moidx reported that the bitstream cached for the `earlgrey_1.0.0` is still from when the branch was originally created, and that tests thus run on an outdated bitstream.

We need to have the latest RTL and ROM, as frozen, in the bitstream cached for the `earlgrey_1.0.0` branch. There's no need for automatic future updates of the cache, though; RTL and ROM won't change for this branch anymore.

We should also document how such a manual bitstream cache update is conducted.

CC @jonmichelson @johngt @GregAC @rswarbrick

Contributor guide

Open the contributing guide

Research direction

No files, tests, or entry points are named. Inspect how the earlgrey_1.0.0 bitstream cache is populated and how tests select it, then verify the cache contains the frozen RTL and ROM and document the manual update procedure.

Written by the indexing model from the issue text.

Assessment

Domain
build-system, documentation, testing-qa
Issue type
Bug
Difficulty
4/5
Estimated time
3-5 days
Activity status
Stale
Clarity
Mostly clear
Newbie friendliness
35/100

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