lowRISC / lowRISC/opentitan

[sival,alert_hander] Clarify alert escalation testpoints

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@matutem is already working on this.

Since Oct 31, 2024.

Component:SiliconValidation IP:alert_handler
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Description

### Description

The `chip_sw_alert_handler_escalation_nmi_reset` testpoint description seems incorrect since it says the test should not trigger escalation levels 1 and 2 since that would mutate the OTP. This is not the case since no OTP update happens on the escalation stages and seems a misunderstanding of the lc_ctrl [escalation handling](https://opentitan.org/book/hw/ip/lc_ctrl/doc/theory_of_operation.html#escalation-handling), which says this results in a "virtual" scrap state.

The `chip_sw_alert_handler_escalations` testpoint does something quite similar but doesn't avoid stages 1 and 2, but it claims to mutate the OTP, which would be incorrect as explained above.

Both these testpoints expect to inspect DUT's internal state, which is optional since from C code we can determine an NMI and a reset were triggered . Determining that state was scrapped could be problematic, but as a fall back that can be tested in DV.

Based on this, I think one of these testpoints can be removed, and the existing C code for the `chip_sw_alert_handler_escalation` DV test could be used, but there are also a number of other tests that also check the escalation flow.

This came up while I reviewed the alert_handler chip-level testplan.

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