[chip-test] flash splicing image into bitstream and run after FPGA is powered on.
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- Dominant language
- SystemVerilog
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Description
### Test point name
test_rom test software
### Host side component
None
### OpenTitanTool infrastructure implemented
None
### Silicon Validation (SiVal)
None
### Emulation Targets
- [ ] None
- [x] CW310
- [ ] Hyperdebug + CW310
### Contact person
_No response_
### Checklist
Dear engineers！！ When I use test_rom to run flash software now, I always need to manually load the test program into OpenTitan's flash using OpenTitantool. How can I achieve automatic testing and running of the program after FPGA is powered on. How to solidify a flash program into a bitstream so that it can be executed immediately after being powered on?
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by tracing the test_rom flow on the CW310 and the OpenTitanTool step currently used to load the flash program. Done would mean the flash software is incorporated into the bitstream and runs automatically after the FPGA is powered on.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100