[ast,verilator] Tune AST model of noise for Verilator simulation

### Description

As discovered in #24184, the `sw/device/tests:entropy_src_fw_observe_many_contiguous_test_sim_verilator` and `sw/device/tests:entropy_src_fw_override_test_sim_verilator` Verilator test targets are failing if given enough timeout. Even though these entropy tests are primarily defined for FPGA, it would be preferable for these tests to still function in the Verilator simulation environment for debugging purposes.

Currently, to allow these tests to pass we must largely reduce the amount of entropy observed, and conditionally provide a much longer timeout to Verilator (see #24528). Verilator is running at a clock frequency of 500 kHz whereas FPGA runs at 24 Mhz, meaning that a 48x increase in timeout is needed to observe similar amounts of entropy. That is, the large increase in timeout is because the rate of the raw noise source (inside the AST) was never tuned for the Verilator simulation.

It would be better if the AST model was tuned for the Verilator simulation so that these tests can pass and be used for debugging purposes without requiring as many device-specific changes to the tests themselves.

Start with the entropy_src_fw_observe_many_contiguous_test_sim_verilator and entropy_src_fw_override_test_sim_verilator targets, then inspect the AST noise model used by Verilator and the timeout or entropy reductions described in #24528. Run both targets with their current settings; done means they pass for debugging without device-specific entropy reductions or a substantially extended Verilator timeout.

Written by the indexing model from the issue text.