lowRISC / lowRISC/opentitan

[prim,fpv] The esc_req_q1 signal is not checked in prim_esc_sender.sv

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Component:FPV IP:prim
Dominant language
SystemVerilog
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Description

### Description

I noticed this when analysing some Jasper results for the prim's testbench. Looking closely, at the RTL, this signal is only used to respond to a ping with `ping_ok_o` on line 207, which looks like this:
```systemverilog
// escalation takes precedence,
// immediately return ok in that case
if ((esc_req_i || esc_req_q || esc_req_q1) && ping_req_i) begin
ping_ok_o = 1'b1;
end
```

In order for the `esc_req_q1` signal to have an effect, we need signals with waves like this:
```
ping_req_i * * 1
esc_req_q1 * * 1
esc_req_q * 1 0
esc_req_i 1 0 0
```
and for the previous lines of the FSM to have run, leaving `ping_ok_o` low.

I think this is probably possible (for example, we might see a `ping_req_i` when we have seen a signal integrity error, and we still want to respond to it).

Contributor guide

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First steps

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  2. Comment on the issue to say you are picking it up — it saves two people doing the same work.
  3. Fork the repository and make your change on a branch.
  4. Open a pull request that references the issue number.

Research direction

Start in prim_esc_sender.sv around line 207 and trace the preceding FSM behavior for ping_req_i, esc_req_i, esc_req_q, and esc_req_q1. Review the prim testbench and the Jasper result that exposed the gap. Done means the esc_req_q1 case is checked and the described signal sequence is covered by verification.

Written by the indexing model from the issue text.

Assessment

Domain
embedded-iot, security
Issue type
Bug
Difficulty
4/5
Estimated time
3-5 days
Activity status
Stale
Clarity
Mostly clear
Newbie friendliness
35/100

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