[hmac,dv] Minor assertion checks
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Component:DV
IP:hmac
- Dominant language
- SystemVerilog
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Description
### Description
- [ ] HMAC core block FIFO size : HMAC core contains a 32x32-bit size FIFO
- [ ] SHA-2 block FIFOs sizes : SHA-2 block contains two time a 8x64-bit size FIFOs (one for the hash and one for the digest)
- [ ] HMAC extra latency : HMAC should introduce a latency equals to 240 extra cycles
- [ ] MSG_LENGTH_LOWER register LSBs : Message length granularity should be in bytes, and these registers express it in bits, so the 3 LSBs from MSG_LENGTH_LOWER should be always zeros
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