lowRISC / lowRISC/opentitan

[hmac,dv] Minor assertion checks

Open
#24,364 2 comments 0 reactions 1 assignee Claimed by @martin-velay View on GitHub
Component:DV IP:hmac
Dominant language
SystemVerilog
Stars
3.6k
Forks
1.1k
Avg merge
2d 22h
Merged PRs (30d)
141

Description

### Description

- [ ] HMAC core block FIFO size : HMAC core contains a 32x32-bit size FIFO
- [ ] SHA-2 block FIFOs sizes : SHA-2 block contains two time a 8x64-bit size FIFOs (one for the hash and one for the digest)
- [ ] HMAC extra latency : HMAC should introduce a latency equals to 240 extra cycles
- [ ] MSG_LENGTH_LOWER register LSBs : Message length granularity should be in bytes, and these registers express it in bits, so the 3 LSBs from MSG_LENGTH_LOWER should be always zeros

Contributor guide

Open the contributing guide

Assessment

This issue has not been assessed yet.

Get new issues in your inbox

A short digest of beginner-friendly GitHub issues.