[test-triage] chip_sw_pwrmgr_random_sleep_all_reset_reqs assertion `noOutstandingReqsAtEndOfSim_A` fails in `tlul_assert.sv`

### Hierarchy of regression failure

Chip Level

### Failure Description

```
Offending '(pend_req[h2d.a_source].pend == 0)'
UVM_ERROR @ 15611.310336 us: (tlul_assert.sv:268) [ASSERT FAILED] pendingReqPerSrc_M
```

### Steps to Reproduce

- GitHub Revision: 07b417ef03dbfc78446dd724f140d250a27cbac1
- dvsim invocation command to reproduce the failure: `./util/dvsim/dvsim.py hw/top_earlgrey/dv/chip_sim_cfg.hjson -i chip_sw_pwrmgr_random_sleep_all_reset_reqs --build-seed 6142445146730822936893044599112392910298048088673599708943858624824800218011 --fixed-seed 114492534761100589938785930582404685653505964686521691658668262871600209521298`

### Tests with similar or related failures

This seems related to the previous issue https://github.com/lowRISC/opentitan/issues/23051 observed for `chip_sw_pwrmgr_deep_sleep_all_reset_reqs`.

Reproduce chip_sw_pwrmgr_random_sleep_all_reset_reqs with the provided dvsim command and revision. Inspect tlul_assert.sv:268 and compare the failure with related issue #23051. Done means the regression no longer reports pendingReqPerSrc_M or the corresponding outstanding-request assertion failure.

Written by the indexing model from the issue text.