[test-triage] i2c_target_hrst
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Since Aug 12, 2024.
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Description
### Hierarchy of regression failure
Block level
### Failure Description
```
UVM_FATAL @ 10047503778 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
```
There is currently a failure rate of approx 50% for this test with the above failure mode.
### Steps to Reproduce
- GitHub Revision: [07b417ef03](https://github.com/lowrisc/opentitan/tree/07b417ef03dbfc78446dd724f140d250a27cbac1)
- dvsim invocation command to reproduce the failure, inclusive of build and run seeds:
`./util/dvsim/dvsim.py hw/ip/i2c/dv/i2c_sim_cfg.hjson -i i2c_target_hrst --build-seed 6142445146730822936893044599112392910298048088673599708943858624824800218011 --fixed-seed 0`
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