[questa] known-good output from passing sims

### Description

Hi,
Since I don't have VCS, I don't have any known-good results to compare against.
I do see my tools flagging zero-delay race conditions at time0, and so I need to get some waveforms so I can reproduce what passes in regression. Verilog has evolved over time on how to handle signals that are initialized at time0, and "@ " on those signals: does the "@" fire at time0, or not? And then some other issues along those lines.

Would it be possible to get any (hopefully all) of the following?
1) logfile for a sim with UVM verbosity set to max
2) the VCD file for the first 100-1000ns for top-level signals and the internals of any clock/reset generators, so I can make sure those are all properly configuring.