lowRISC / lowRISC/opentitan

[spi_device] SPI Device SRAM does not support byte-writes or read access

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#24,220 2 comments 0 reactions 1 assignee Claimed by @hcallahan-lowrisc View on GitHub
Type:FutureRelease
Dominant language
SystemVerilog
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Description

### Description

Non-word writes to the SPI Device SRAM cause a store fault. We can write unaligned data by manually masking the bits, but in the a0 [revision](https://github.com/lowRISC/opentitan/blob/master/hw/ip/spi_device/data/spi_device.hjson#L1557), there doesn't appear to be read access to the egress buffer, so this would require maintaining a shadow copy of the SRAM. See the Rust code below for an example to reproduce.

```rust
const SPI_DEVICE_BASE_ADDR: usize = 0x40050000;
const MAILBOX_RAW_ADDRESS: usize = SPI_DEVICE_BASE_ADDR + 0x1000 + 0x800;
const MAILBOX_SIZE: usize = 1024;

fn reset_mailbox(&self) {
// SAFETY: reference to mailbox destroyed on function end
unsafe { slice::from_raw_parts_mut(MAILBOX_RAW_ADDRESS as *mut _, MAILBOX_SIZE) }.fill(0);
fence();
}
```

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