[DMA] DMA always performs 4-byte TLUL reads - regardless of transfer width

Nobody has claimed this yet.

### Description

The DMA accesses the TLUL XBARs using a tlul_adapter_host from the OT-infrastructure to perform these bus requests. The DMA further supports a configurable access granularity of 1-byte, 2-byte, or 4-byte.

The tlul_adapter_host however, when performing a READ operation, always reads a 4-byte value, regardless of the DMA configuration.

When looking into the code of tlul_adapter_host.sv , the a_mask field of the bus is responsible to mask actual data we want to read and to support smaller bus requests. However, a_mask is set to tl_be, which is set to the following value:

assign tl_be = ~we_i ? {top_pkg::TL_DBW{1'b1 : be_i;}}

Essentially, this means for read requests, tl_be}}is set to {{1111, which means it always reads 4-byte. It further only a Get}}request and no {{GetPartialData opcode on the bus.

In the DMA, this is problematic, because the handshake mode might access MMIO devices, that have a smaller register width. Reading a 32-bit value can lead to undefined behavior. If Inline hashing is active, the last word might not be padded correctly, thus leading to a wrong hash digest.

Start by reading tlul_adapter_host.sv and the DMA access-granularity and handshake path described in the issue. Trace read opcode and byte-mask behavior for 1-, 2-, and 4-byte transfers; done means MMIO reads honor the configured width and the final inline-hash word is handled correctly.

Written by the indexing model from the issue text.