[top_earlgrey,cdc] Complete CDC signoff
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Component:CDC
TOP:earlgrey
- Dominant language
- SystemVerilog
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Description
- Go through remaining errors and warnings in iDebug and review them with designers.
- Preferably tune tool settings such that no waivers are needed.
- Add waivers for remaining errors and warnings.
- Remove
ast_clks_bypfrom the list of black-boxed modules. - Analyze expressions that are currently black-boxed. Increase
ri_max_total_range_bitsif necessary, and ideally find a way to enable this on machines that have enough RAM.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by reviewing the remaining errors and warnings in iDebug with the designers. Then inspect the black-boxed module list for ast_clks_byp and the expressions affected by ri_max_total_range_bits. Done means resolving or waiving all signoff issues, removing ast_clks_byp from black-boxing, and enabling broader range analysis where machine RAM permits.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, tooling
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 25/100