lowRISC / lowRISC/opentitan

[spi_host, dv] Ensure the TB checks for incorrect masks and clears ACCESINVAL error accordingly

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#24,198 0 comments 0 reactions 1 assignee Claimed by @antmarzam View on GitHub
Component:DV IP:spi_host
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SystemVerilog
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Description

### Description

The spi-host TB doesn't currently do error_status.accessinval verification. This issue is meant to track ACCESSINVAL stimulus needed, checking and coverage.

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