[spi_host] ACCESSINVAL error set, tl-ul bus error not signalled.

Nobody has claimed this yet.

### Description

When writing to the TX FIFO only 1/2/4 bytes masks are allowed, any other combination means the write will be discarded but no error is signalled back at the TL-UL interface. The valid strobes are defined [here](https://github.com/lowRISC/opentitan/blob/fdfa12db04f7dd13f9a5bbe6190c79435a6ce1d6/hw/ip/spi_host/rtl/spi_host.sv#L362-L378)

You can see an example below, where the mask is 0x7, which causes an ACCESSINVAL error, but the TL-UL bus doesn't raise the `d_error` signal:

Is this the intended behaviour?

cc: @a-will / @vogelpi / @andreaskurth / @hcallahan-lowrisc

Start with hw/ip/spi_host/rtl/spi_host.sv, especially the valid strobe definitions at lines 362-378, and trace how an invalid TX FIFO write reaches the TL-UL response. Confirm whether ACCESSINVAL should assert d_error; completion requires an agreed behavior and coverage for the 0x7 mask case.

Written by the indexing model from the issue text.