[usbdev] Packet reception logic is unaware of Resume Signaling
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- SystemVerilog
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Description
### Description
The packet reception logic in `usb_fs_rx` is unaware of Resume Signaling and in consequence `pkt_start_o` becomes asserted at the start of Resume Signaling (J->K transition), and `pkt_end_o` becomes asserted at the end of the signaling upon entering SE0 for a number of bit intervals.
This also happens when (as in one DV sequence) the USB transitions from a Bus Reset state to Resume Signaling (not something that should happen on a physical USB connection). In this case since the DV sequence has never previously transmitted any valid data, the `full_pid` data in the reception logic holds an invalid PID and leads to a spurious assertion of `rx_pid_err` interrupt state bit/line.
The possible ramifications of this should be considered.
Current assessment: Minor.
It should not cause any issues beyond producing spurious diagnostic reports since `packet_valid_(d|q)` assertion never occurs, so none of the state machines should ever receive an indication of packet reception. It would be worth tidying this up along with the other packet reception changes.
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Assessment
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