[test-triage] `aes_unmasked`:`aes_stress_all` assert failure

Hierarchy of regression failure

Block level

Failure Description

* `xmsim: *E,ASRTST (/home/eb/opentitan/scratch/HEAD/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_*/r
tl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS)` has 1 fa
ilures:
    * Test aes_stress_all has 1 failures.
        * 0.aes_stress_all.101273780368967591265181953828150782839460977122418537366855771075064562735320\
          Line 51234, in log /home/eb/opentitan/scratch/HEAD/aes_unmasked-sim-xcelium/0.aes_stress_all/lates
t/run.log

                xmsim: *E,ASRTST (/home/eb/opentitan/scratch/HEAD/aes_unmasked-sim-xcelium/default/src/lowri
sc_ip_aes_1.0/rtl/aes_core.sv,987): (time 706395298 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscD
ataOut has failed (2 cycles, starting 706360815 PS)
                      ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                                 |
                xmsim: *E,ASRTST (/home/eb/opentitan/scratch/HEAD/aes_unmasked-sim-xcelium/default/src/lowri
sc_ip_aes_1.0/rtl/aes_core.sv,993): (time 706395298 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscI
v has failed (2 cycles, starting 706360815 PS)
                UVM_ERROR @ 706395298 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

Steps to Reproduce

• GitHub Revision: 974aaab627
• dvsim invocation command to reproduce the failure, inclusive of build and run seeds:
  ./util/dvsim/dvsim.py hw/ip/aes/dv/aes_unmasked_sim_cfg.hjson -i aes_stress_all --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879 --fixed-seed 101273780368967591265181953828150782839460977122418537366855771075064562735320

Tests with similar or related failures

No response