lowRISC / lowRISC/opentitan

[test-triage] `i2c_host_stress_all` low pass-rate

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#24,066 3 comments 0 reactions 1 assignee Claimed by @hcallahan-lowrisc View on GitHub
Component:TestTriage IP:i2c
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Description

### Hierarchy of regression failure

Block level

### Failure Description

Multiple failure sources in the latest regression, but this was the most common:
```
UVM_ERROR @ 38405032791 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
```

### Steps to Reproduce

- GitHub Revision: 974aaab627
- dvsim invocation command to reproduce the failure, inclusive of build and run seeds:
`./util/dvsim/dvsim.py hw/ip/i2c/dv/i2c_sim_cfg.hjson -i i2c_host_stress_all --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879 --fixed-seed 111351861029607319840208042477550323195458624262667788092371830570225893891502`

### Tests with similar or related failures

54060242010632769836666320237261266906268616954605287882421647600191088640353

Contributor guide

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Assessment

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