[sw,dv] Backdoor write from DV (`sw_symbol_backdoor_overwrite`) does not work for main SRAM
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- SystemVerilog
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Description
When DV code calls `sw_symbol_backdoor_overwrite` on a symbol that is located in main SRAM (such as a non-`const` global variable declared in C code), the updated value of the variable might not be visible to SW running on Ibex.
One instance of this problem caused this spinwait in the `rv_dm_access_after_wakeup` test to not exit
https://github.com/lowRISC/opentitan/blob/33e462e0c0daa8ec60fabc6392f12ae6e5f403b8/sw/device/tests/rv_dm_access_after_wakeup.c#L95
When the variable is instead located in flash, which can be achieved by qualifying a global variable as `const` in C code, the value written by DV code is visible to SW code running on Ibex as expected. FPGA tests, on the other hand, need a variable that can be modified by SW and thus cannot be located in flash (which is write-protected by PMP), so a separate variable is needed (see [comment below](https://github.com/lowRISC/opentitan/issues/23926#issuecomment-2210351157)).
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start with sw/device/tests/rv_dm_access_after_wakeup.c around the spinwait and trace how sw_symbol_backdoor_overwrite handles symbols in main SRAM versus flash. Reproduce the failure in the DV test, then verify that a main-SRAM backdoor write is visible to Ibex and that the FPGA case still has a SW-modifiable variable.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- c
- Domain
- embedded-iot, testing
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 35/100