[rom,e2e] enforce banner check in FPGA test
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Component:RomExt/E2e/Test
SW:ROM
Type:Cleanup
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- SystemVerilog
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Description
The following two ROM E2E tests in DV check the ROM banner that is printed:
1. shutdown_exception_c
2. shutdown_output
We should align the FPGA tests to check the same output so we can catch a change in CI and not have to wait for the DV regression to fail to notice the issue. This comes from a review comment originally posted by @moidx in https://github.com/lowRISC/opentitan/pull/23804#pullrequestreview-2146552655_
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