[dvsim] Issue with Gate Level Simulation using SDF File

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Hi there,

For fusesoc in dvsim, it will copy the source systemverilog codes into `src` folder and use the copied files for compiling.

But for gate level simulation(netlist already obtained, just replace the file list and add some command) on vcs, the sdf function `$sdf_annotate ( “sdf_file”,,,,,, “scale_type”);` has a very special requirement:
```
“sdf_file”:
The full or relative path of the SDF file. This argument is required and must be in quotation marks. You can specify the file name with the +sdf_file plus option on the command line.
```
which means that if you use this function in tb, the passed in `sdf_file` should be a raw string instead of a string variable.

In this case, the fusesoc will change the relative path during compiling and hence a FileNotFound error regarding sdf file will occur.

Start with the dvsim FuseSoC source-copy and compilation flow described in the issue, then reproduce the VCS gate-level simulation using the `$sdf_annotate` entry point. Done means the SDF file remains resolvable after compilation and the simulation no longer reports a FileNotFound error.

Written by the indexing model from the issue text.