[fpga] Tech-specific implementation of `prim_flop_2sync`

We currently use the generic implementation of `prim_flop_2sync` on the FPGA. At least for certain use cases, it could be beneficial (higher MTBF for synchronization failures) to use specialized cells such as `XPM_CDC_SINGLE` (see [7 Series FPGA Libraries Guide](https://docs.amd.com/r/en-US/ug953-vivado-7series-libraries/XPM_CDC_SINGLE) and [UltraScale Architecture Libraries Guide](https://docs.amd.com/r/en-US/ug974-vivado-ultrascale-libraries/XPM_CDC_SINGLE)).

Start by locating the generic implementation of `prim_flop_2sync` and examining how FPGA-specific primitives are selected. Read the linked AMD 7 Series and UltraScale Libraries Guide entries for `XPM_CDC_SINGLE`; done should provide a specialized FPGA implementation for the relevant synchronization use cases.

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