[pinmux] Earl Grey open drain

### Description

In #22802 Miguel lists the following NuvoTitan pins as having true open drain capability: IOA[6-8], IOB[9-12], IOC[10-12], IOR[8-13]. However, on the Z1 engineering silicon, I see open drain capability on B8 as well. (I have not tested all pins, this was just one random discrepancy.) We should document exactly which set of pins have open drain capability.

Also, I would like to know if it ever is advantageous to enable "virtual open drain" on a NuvoTitan pad which has true open drain capability. If not, then I do not understand why MIO_PAD_ATTR has both "true open drain" and "virtual open drain" bits, as opposed to having a single "open drain" bit, which for some pads are routed to the vendor's "true open drain" enable signal, and for other pads are routed to the vendor's "virtual open drain" enable signal (with the other vendor signal being permanently deasserted, since it does not do anything anyway).

If we are trying to make a reusable open design, which can be used by multiple vendors, I do not think we should expose the fact that Nuvoton's technology happens to distinguish between virtual and true open drain. I realize this is probably to late and too risky to address for A1, but at the very least, the NuvoTitan documentation should specify which pads support true open drain, and what is the effect of enabling one or the other kind of open drain on either kinds of pads.