[rv_dm] dmcontrol.haltreq should always read as 0
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Component:RTL
IP:rv_dm
Triage Priority
Type:Bug
- Dominant language
- SystemVerilog
- Stars
- 3.6k
- Forks
- 1.1k
- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
### desc
The RISC-V spec (v0.13.2) defines the dmcontrol.haltreq bit with access "W" (Section 3.12.2), which is defined as "Write-only. When read this field returns 0" (Table 1.2). However, the current implementation allows this bit to be read as 1 after a write sets it to 1.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by locating the rv_dm implementation of dmcontrol.haltreq and the tests covering dmcontrol reads and writes. Compare its behavior with the RISC-V v0.13.2 Section 3.12.2 and Table 1.2 requirements; done means haltreq reads as 0 even after writing it to 1, with regression coverage.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot
- Issue type
- Bug
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Activity status
- Active
- Clarity
- Mostly clear
- Newbie friendliness
- 68/100