[ROM] consider checking FIFO depth before sending data to HMAC/KMAC interfaces
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Type:FutureRelease
- Dominant language
- SystemVerilog
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Description
### Description
In the past we had the assumption that any FIFO overflows would be prevented by stalling the bus. This is not an ideal behavior given that we could end up in a situation where incoming interrupts can cause deadlock scenarios.
Adding to the ROM milestone for initial triage.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
No source file, test, or entry point is named. Start by tracing the ROM paths that send data to the HMAC/KMAC interfaces and inspect how FIFO fullness and bus stalling are currently handled; done should prevent FIFO overflow without creating the described interrupt-related deadlock scenario.
Written by the indexing model from the issue text.
Assessment
- Domain
- cryptography
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 32/100