[test-triage] Chip_sw_uart_tx_rx_bootstrap timeout
Nobody has claimed this yet.
- Dominant language
- SystemVerilog
- Stars
- 3.6k
- Forks
- 1.1k
- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
### Hierarchy of regression failure
Chip Level
### Failure Description
Timeout
### Steps to Reproduce
- GitHub Revision: [9656691e03](https://github.com/lowrisc/opentitan/tree/9656691e037c6fc5b87369d8fbab300cb34dff80)
- dvsim invocation command to reproduce the failure, inclusive of build and run seeds:
./util/dvsim/dvsim.py hw/top_earlgrey/dv/chip_sim_cfg.hjson -i chip_sw_uart_tx_rx_bootstrap --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439 --fixed-seed 38902495902850271867553058495145156207109662916179471927802333451347076119242 --waves fsdb
- Kokoro build number if applicable
### Tests with similar or related failures
- [ ] Test_name_1
- [ ] Test_name_2
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by rerunning the provided util/dvsim/dvsim.py command for chip_sw_uart_tx_rx_bootstrap at revision 9656691e03 with the recorded build and run seeds. Inspect the resulting timeout in hw/top_earlgrey/dv/chip_sim_cfg.hjson and the test's simulation output; done means identifying and resolving the regression so the test completes successfully.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, testing-qa
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100