[test-triage] Spi host csr_spinwait (status.active) timeout
@antmarzam is already working on this.
Since May 3, 2024.
- Dominant language
- SystemVerilog
- Stars
- 3.6k
- Forks
- 1.1k
- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
### Hierarchy of regression failure
Block level
### Failure Description
UVM_FATAL @ 154487115457 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x55c79bd4) == 0x0
UVM_INFO @ 154487115457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
### Steps to Reproduce
- GitHub Revision: [ecd9f08747](https://github.com/lowrisc/opentitan/tree/ecd9f08747a0211848e927aa352046608f61e226)
- util/dvsim/dvsim.py hw/ip/spi_host/dv/spi_host_sim_cfg.hjson -r 1 -v d --run-timeout-mins 12 -i spi_host_smoke -s 1235650334688678634647264155014628413788613701393407177139208252719966856963
-
### Tests with similar or related failures
- [ ] spi_host_smoke.20895908292026024735497159656586769349430635476511730068939528370707065927986
- [ ] spi_host_status_stall.107551862686388589245117855046971315418230458029015449110319754458266211834497
- [ ] spi_host_smoke.3708128113627781838430850913386980843783318534377996661422211308217293011831
- [ ] spi_host_stress_all.4577804394977826170289019831919585580182886343987067209780060118870024031312
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Assessment
This issue has not been assessed yet.