[ram_2p] Document and assert on read/write behavior
Nobody has claimed this yet.
- Dominant language
- SystemVerilog
- Stars
- 3.6k
- Forks
- 1.1k
- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
_Originally posted by @cdgori in https://github.com/lowRISC/opentitan/issues/2201#issuecomment-628121556_
A side comment - some 2P memories will have issues (undefined or strange behavior) when one writes and reads the same address across the two ports. Or we would have to manually implement the bypassing of write-to-read if needed/expected.
The generic prim seems to accept this condition, not sure if we want to leave that as-is?
---
We should:
* Document the expected behavior around the read/write behavior of the 2p SRAM.
* Assert on conditions which are undefined.
Ideally, we find a behavior which are a good "common denominator", it's always easier to provide a wrapper than it is to generate new memories with a memory compiler.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by reviewing the generic prim's 2P SRAM behavior for reads and writes to the same address across both ports. Establish a common-denominator behavior, document the expected cases, and add assertions for conditions that remain undefined.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot
- Issue type
- Documentation
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100