[aes] V3 Signoff
Open
Nobody has claimed this yet.
Component:DV
IP:aes
Type:Signoff
- Dominant language
- SystemVerilog
- Stars
- 3.6k
- Forks
- 1.1k
- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
### Description
_No response_
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
The issue names only AES V3 signoff and provides no files, tests, entry points, scope, or acceptance criteria. Start by locating the project’s AES V3 design and signoff documentation, then identify the required review or validation steps; the issue is done only when those signoff requirements are defined and satisfied.
Written by the indexing model from the issue text.
Assessment
- Domain
- cryptography, embedded-iot, security
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 10/100