[top_darjeeling,clkmgr] Clock Measurement is wrong for Darjeeling
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Component:Darjeeling
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- SystemVerilog
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Description
Darjeeling runs at 1000/250/62.5 MHz. The clkmgr has inbuild measurement primitives. These are however still configured for the Earlgrey frequencies (96/48/24 MHz) like following example shows. (Cnt = 480)
/cc @neeraj-rv @andreaskurth
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start with hw/top_darjeeling/ip/clkmgr/rtl/autogen/clkmgr.sv at lines 602-623 and inspect how the clock measurement primitives are configured. Compare those Earlgrey values with Darjeeling's 1000/250/62.5 MHz frequencies. Done means Darjeeling's measurement configuration uses the correct frequencies instead of the values shown in the issue.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot
- Issue type
- Bug
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100