[i2c] Implement a digital 50ns Glitch/Spike Filter

Description

I2C requires a fixed 50ns glitch suppression filter as part of its electrical specification (t_sp) for FM/FM+, which facilitates co-existence on a bus with I3C devices, among other things.
For EarlGrey, this is implemented as a static filter in the IO block (see this comment).

To improve compatibility and flexibility, we should consider implementing this filter digitally in the I2C block itself.
This could be a simple shift-register based design, which is parameterized or programmable to function at different input clock frequencies.
Any latency added by this filter should be factored into the logic which anticipates a Target-Receiver stretching the clock. If the filter is located within the I2C block, this can easily be incorporated into the implementation added in #21813 (comment).

Also see #17456, which discusses the general concern of noise on the I2C bus.