[dvsim] Various questions

### Description

https://opentitan.org/book/hw/top_earlgrey/index.html says to execute this command, and it executes successfully.
NOTE: the HTML does not say which directory to run in, it would be useful if the user did not have to figure it out.

cd $(REPO_TOP)/hw/top_earlgrey; ../..//util/topgen.py -t data/top_earlgrey.hjson -o . -v

https://opentitan.org/book/hw/top_earlgrey/dv/index.html says to execute this command to simulate the UART.
cd $(REPO_TOP);./util/dvsim/dvsim.py hw/top_earlgrey/dv/chip_sim_cfg.hjson -i chip_sw_uart_tx_rx

However, the following errors occur:
INFO: [dvsim] [proj_root]: /opentitan/Ubuntu1/opentitan
INFO: [SimCfg] [scratch_path]: [chip] [/opentitan/Ubuntu1/opentitan/scratch/master/chip_earlgrey_asic-sim-vcs]
ERROR: [Modes] Test "chip_plic_all_irqs" added to regression "xcelium_ci_0" not found!
ERROR: [Modes] Test "chip_sw_aes_force_prng_reseed" added to regression "V2" not found!
ERROR: [Modes] Test "chip_plic_all_irqs" added to regression "V2" not found!
ERROR: [Modes] Test "chip_sw_aes_prng_reseed" added to regression "V2" not found!
INFO: [StatusPrinter] [ legend ]: [Q: queued, D: dispatched, P: passed, F: failed, K: killed, T: total]
INFO: [StatusPrinter] 00:00:00 [ build ]: [Q: 0, D: 1, P: 0, F: 0, K: 0, T: 1] 0% chip:default
WARNING: [Deploy] chip:default: Job runtime not found in the log. Using dvsim-maintained job_runtime instead.
ERROR: [Scheduler] [00:00:01]: [build]: [status] [chip:default: F]
INFO: [StatusPrinter] 00:00:01 [ build ]: [Q: 0, D: 0, P: 0, F: 1, K: 0, T: 1] 100%
INFO: [StatusPrinter] 00:00:01 [ run ]: [Q: 0, D: 0, P: 0, F: 0, K: 5, T: 5] 100%
INFO: [FlowCfg] [results]: [chip]:

I am guessing that there are some intermediate steps required for generating the rest of the RTL, but it is not obvious to me what command(s) are required.

Start with the linked top_earlgrey and top_eargrey/dv documentation pages, then inspect util/topgen.py, util/dvsim/dvsim.py, and hw/top_earlgrey/dv/chip_sim_cfg.hjson. Reproduce both commands and determine the required working directory or generation steps. Done means the documentation explains the prerequisites and commands clearly and the UART simulation runs without the reported missing-test errors.

Written by the indexing model from the issue text.