[i2c,rtl] Compress FMT FIFO entries

Nobody has claimed this yet.

When moving all i2c FIFOs into a single SRAM, which is one option being explored for https://github.com/lowRISC/opentitan/issues/22159, the FMT FIFO is problematic as it has more bits per entry (13) than all the other FIFOs (at most 10). The current entry encoding, where each flag has its own bit

| Bits | Type | Reset | Name | Description |
|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------|
| 12 | wo | 0x0 | NAKOK | Do not signal an exception if the current byte is not ACK'd |
| 11 | wo | 0x0 | RCONT | Do not NACK the last byte read, let the read operation continue |
| 10 | wo | 0x0 | READB | Read BYTE bytes from I2C. (256 if BYTE==0) |
| 9 | wo | 0x0 | STOP | Issue a STOP condition after this operation |
| 8 | wo | 0x0 | START | Issue a START condition before transmitting BYTE. |
| 7:0 | wo | 0x0 | FBYTE | Format Byte. Directly transmitted if no flags are set. |

might be a waste of space. (I think the CSR format is fine and doesn't have to change, but the encoding for storage in the FIFO can be compacted.)

Could a more compact encoding, such as the following, work?
| `wdata[9:8]` | `wdata[7:0]` | effect |
|------------|-----------------------|----------------------------------------------------------------------------------------------------------------------------------------------------------|
| `2'b00` | *fbyte* | write *fbyte* |
| `2'b01` | *fbyte* | write *fbyte* w/o exception if not ACK'd |
| `2'b10` | *fbyte* | read *fbyte* bytes |
| `2'b11` | {`8'h00`, `8'h01`, `8'h02`} | depending on `wdata[7:0]`, generate a Start (`8'h00`) or Stop (`8'h01`) condition or continue reading after having received all bytes (`8'h02`, current RCONT flag) |

(If compressing FMT FIFO entries to 10 bit is impossible, we could still use a 10-bit-wide deep SRAM plus 3x64 FFs 'on the side' to complement the FMT data.)

Start by reading issue 22159 and tracing the I2C FMT FIFO storage encoding described here, including how the CSR format maps to FIFO entries. Determine whether the proposed 10-bit encoding preserves all listed effects; done means a compact implementation is shown to work, or the alternative SRAM-plus-side-register design is justified.

Written by the indexing model from the issue text.