lowRISC / lowRISC/opentitan

[i2c,dv] Re-think monitor DV for detecting S/Sr/P conditions

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#21,887 3 comments 0 reactions 1 assignee View on GitHub

@hcallahan-lowrisc is already working on this.

Since Apr 2, 2024.

Component:DV IP:i2c
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Description

Description

As part of #21765, some of the monitor DV code was weakened to make the detection of START/RSTART/STOP conditions less stringent. The way the monitor is currently constructed, we are trying to observe the derived timing parameters in terms of setup/hold cycles, which currently leads to a stacking of tolerances that is brittle. Removing the double-counted t_f was enough to break these checks, and instead of noticing any timing violations the monitor loses its lock on the bus traffic and we see a failure way down the line in the simulation. This is not a great developer experience, and is tricky to debug.
This issue tracks the re-enablement of these checks, preferably in a more robust way for future I2C developments.

Edit: #23078 split-out from this issue, to de-prioritise the refactoring-part of this issue.

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