> Modifying HW top-level module files

### Description

Hello, how can I modify the connections of various modules under chip_earlgry_310? For example, the signals between Top_earlgrey and AST. What should I do ? I see the introduction saying that the [chip_earlgry_310.sv](http://chip_earlgry_310.sv/) file is automatically generated?

Start with the introduction referenced in the issue and inspect chip_earlgry_310.sv, along with the connections between Top_earlgrey and AST. Done means documenting the supported way to modify these connections despite the file being automatically generated.

Written by the indexing model from the issue text.