[sival,triag] Some SiVal ROM_EXT are broken

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### Description

The following tests have been found to be broken in `//hw/top_earlgrey:fpga_cw310_sival_rom_ext` execution environment. See #21580 for details. This issue tracks the lists for further triaging.
- `edn_kat_fpga_cw310_sival_rom_ext` -> fixed
- `flash_ctrl_mem_protection_test_fpga_cw310_sival_rom_ext`
- `flash_ctrl_test_fpga_cw310_sival_rom_ext`
- `pmp_smoketest_tor_fpga_cw310_sival_rom_ext`
- `rv_core_ibex_address_translation_test_fpga_cw310_sival_rom_ext`
- `sram_ctrl_execution_test_fpga_cw310_sival_rom_ext`
- `uart_tx_rx_test_fpga_cw310_sival_rom_ext`
- `keymgr_test_fpga_cw310_sival_rom_ext`
- `boot_data_functest_fpga_cw310_sival_rom_ext`
- `irq_asm_functest_fpga_cw310_sival_rom_ext`
- `alert_functest_fpga_cw310_sival_rom_ext`
- `keymgr_functest_fpga_cw310_sival_rom_ext`
- `rnd_functest_fpga_cw310_sival_rom_ext`
- `rstmgr_functest_fpga_cw310_sival_rom_ext`
- `watchdog_functest_fpga_cw310_sival_rom_ext`
- `mod_exp_otbn_functest_hardcoded_fpga_cw310_sival_rom_ext`
- `rsa_verify_functest_fpga_cw310_sival_rom_ext`
- `sigverify_dynamic_functest_hardcoded_fpga_cw310_sival_rom_ext`
- `chip_power_idle_load_fpga_cw310_sival_rom_ext`
- `chip_power_sleep_load_fpga_cw310_sival_rom_ext`
- `csrng_edn_concurrency_test_fpga_cw310_sival_rom_ext` -> fixed
- `csrng_kat_test_fpga_cw310_sival_rom_ext` -> fixed
- `entropy_src_csrng_test_fpga_cw310_sival_rom_ext` -> fixed
- `entropy_src_edn_reqs_test_fpga_cw310_sival_rom_ext` -> fixed
- `flash_ctrl_clock_freqs_test_fpga_cw310_sival_rom_ext`
- `flash_ctrl_ops_test_fpga_cw310_sival_rom_ext`
- `keymgr_key_derivation_test_fpga_cw310_sival_rom_ext`
- `keymgr_sideload_aes_test_fpga_cw310_sival_rom_ext`
- `keymgr_sideload_kmac_test_fpga_cw310_sival_rom_ext`
- `lc_ctrl_otp_hw_cfg0_test_fpga_cw310_sival_rom_ext`
- `otp_ctrl_smoketest_fpga_cw310_sival_rom_ext`
- `pmp_smoketest_napot_fpga_cw310_sival_rom_ext`
- `sram_ctrl_sleep_sram_ret_contents_scramble_test_fpga_cw310_sival_rom_ext`
- `aes_kwp_sideload_functest_fpga_cw310_sival_rom_ext`
- `aes_sideload_functest_fpga_cw310_sival_rom_ext`
- `ecdh_p256_sideload_functest_fpga_cw310_sival_rom_ext`
- `ecdsa_p256_sideload_functest_fpga_cw310_sival_rom_ext`
- `kdf_kmac_sideload_functest_hardcoded_fpga_cw310_sival_rom_ext`
- `kmac_sideload_functest_hardcoded_fpga_cw310_sival_rom_ext`
- `pwrmgr_random_sleep_all_reset_reqs_test_fpga_cw310_sival_rom_ext`
- `pwrmgr_all_reset_reqs_test_fpga_cw310_sival_rom_ext`

There are some common patterns but each test needs to be investigated:
- some are enabled in ROM_EXT but cannot actually run in ROM_EXT because some registers are locked: those should disable the `//hw/top_earlgrey:fpga_cw310_sival_rom_ext` and enable the `//hw/top_earlgrey:fpga_cw310_sival` exec env instead
- some make assumptions about the OTP values in `//hw/top_earlgrey:fpga_rom_with_fake_keys` but the values in the sival ROM_EXT are different

The corresponding sival issues should be reopened.

Start with the failing test labels under //hw/top_earlgrey:fpga_cw310_sival_rom_ext and read #21580 for the existing context. Investigate each test's execution environment and OTP assumptions, comparing the ROM_EXT and fpga_cw310_sival configurations. Done means each listed test is fixed or assigned to the appropriate environment, and the corresponding SiVal issues are reopened.

Written by the indexing model from the issue text.