[chip-test] chip_sw_csrng_fuse_en_sw_app_read

### Test point name

chip_sw_csrng_fuse_en_sw_app_read

### Host side component
Rust?

### Opentitantool infrastructure implemented
Yes

### Silicon Validation (SiVal)

Yes

### Emulation targets
- [ ] None
- [ ] CW310
- [ ] Hyperdebug + CW310

### Contact person

### Checklist
Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.
- [ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
- [ ] Device-side (C) component developed
- [ ] Bazel build rules developed
- [ ] Host-side component developed
- [ ] Test added to dvsim nightly regression (and passing at time of checking)
- [ ] For SiVal test cases, test is running relevant FPGA or silicon regression

Start by checking whether an existing test already covers the chip_sw_csrng_fuse_en_sw_app_read test point. Then inspect the device-side C, Bazel, host-side Rust, and dvsim nightly regression work needed for this checklist. Done means the required components are developed, the test passes in nightly regression, and relevant FPGA or silicon validation is running.

Written by the indexing model from the issue text.