[chip-test] chip_sw_otp_prim_tl_access

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### Test point name

chip_sw_otp_prim_tl_access

### Host side component
Rust?

### Opentitantool infrastructure implemented
Yes

### Silicon Validation (SiVal)

Yes

### Emulation targets
- [ ] None
- [ ] CW310
- [ ] Hyperdebug + CW310

### Contact person

### Checklist
Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.
- [ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
- [ ] Device-side (C) component developed
- [ ] Bazel build rules developed
- [ ] Host-side component developed
- [ ] Test added to dvsim nightly regression (and passing at time of checking)
- [ ] For SiVal test cases, test is running relevant FPGA or silicon regression

Start by locating the chip_sw_otp_prim_tl_access test point and the existing OpenTitan test infrastructure it should use. Check whether an existing test covers it, then work through the device-side, Bazel, host-side, nightly dvsim, and SiVal checklist items; done means the relevant regressions are running and passing.

Written by the indexing model from the issue text.